Phase shifter and multibit phase shifter

ABSTRACT

A phase shifter includes an FET  2   a  having its drain electrode connected to an input/output terminal  1   a ; and FET  2   b  having its drain electrode connected to the source electrode of the FET  2   a  and its source electrode connected to an input/output terminal  1   b ; and FET  2   c  having its drain electrode connected to the source electrode of the FET  2   a ; and an inductor  3   a  having its first terminal connected to the source electrode of the FET  2   c  and its second terminal connected to a ground. It can reduce the insertion loss by narrowing the gate width of the FET  2   a , and carries out the phase shift of a high-frequency signal with suppressing the reflection.

This application is the national phase under 35 U.S.C. § 371 of PCTInternational Application No. PCT/JP02/02929 which has an Internationaltiling date of Mar. 26, 2002, which designated the United States ofAmerica.

TECHNICAL FIELD

The present invention relates to a phase shifter and multiple-bit phaseshifter for electrically varying the pass phase of a signal in themicrowave band or millimeter-wave band.

BACKGROUND ART

FIG. 1 is a circuit diagram showing a configuration of a conventionalphase shifter disclosed in “2000 IEEE Microwave Theory and TechniqueSymposium Digest”, for example. In FIG. 1, reference numerals 1 a and 1b each designate an input/output terminal; 2 a and 2 b each designate anFET; 3 a, 3 b and 3 c each designate an inductor; 4 a and 4 c eachdesignate a resistor; 5 a and 5 b each designate a control signalterminal; and the reference numeral 8 designates a capacitor.

Next, the operation will be described.

FIG. 2 is an equivalent circuit showing the operation of theconventional phase shifter.

First, consider a case where the control signal terminal 5 a is suppliedwith a negative voltage that will pinch off the FET 2 a, and the controlsignal terminal 5 b is supplied with a zero or positive voltage thatwill bring the FET 2 b into conduction. In this case, the phase shifteris represented by the equivalent circuit as shown in FIG. 2.

Here, if the sum of the OFF-state capacitance of the FET 2 a and thecapacitance of the capacitor 8 is very small, and the ON-stateresistance of the FET 2 b is small, the circuit operates as a π-typehigh-pass filter.

Next, consider a case where the control signal terminal 5 a is suppliedwith a zero or positive voltage that will bring the FET 2 a intoconduction, and the control signal terminal 5 b is supplied with anegative voltage that will pinch off the FET 2 b.

FIG. 3 is an equivalent circuit showing the operation of theconventional phase shifter. It shows an equivalent circuit of the phaseshifter described above.

Here, if the ON-state resistance of the FET 2 a is small, and if theOFF-state capacitance of the FET 2 b and inductor 3 c cause parallelresonance at a desired frequency, the inductors 3 a and 3 b have only asmall effect. Thus, the circuit is equivalent to a through circuit.

Although the high-pass filter advances the phase, the through statelittle varies the pass phase. Accordingly, switching the control signalsmakes it possible to electrically switch the pass phase from theinput/output terminal 1 a to the input/output terminal 1 b.

With the foregoing configuration, the conventional phase shifter has aproblem of its considerable loss because of the reduced gate width ofthe FET 2 a, which is designed to curb the effect of the OFF-statecapacitance of the FET 2 a in the pinched-off state.

The present invention is implemented to solve the foregoing problem.Therefore an object of the present invention is to provide a compact andlow-loss phase shifter and multiple-bit phase shifter.

DISCLOSURE OF THE INVENTION

According to a first aspect of the present invention, there is provideda phase shifter comprising: a first field effect transistor having itsfirst channel electrode connected to a first input/output terminal; asecond field effect transistor having its first channel electrodeconnected to a second channel electrode of the first field effecttransistor, and its second channel electrode connected to a secondinput/output terminal; a third field effect transistor having its firstchannel electrode connected to the second channel electrode of the firstfield effect transistor; and an inductor having its first terminalconnected to a second channel electrode of the third field effecttransistor, and its second terminal connected to a ground.

Thus, it offers an advantage of being able to implement a compact andlow-loss phase shifter.

According to a second aspect of the present invention, there is provideda phase shifter comprising: a first field effect transistor having itsfirst channel electrode connected to a first input/output terminal; asecond field effect transistor having its first channel electrodeconnected to a second channel electrode of the first field effecttransistor, and its second channel electrode connected to a secondinput/output terminal; an inductor having its first terminal connectedto the second channel electrode of the first field effect transistor;and a third field effect transistor having its first channel electrodeconnected to a second terminal of the inductor, and its second channelelectrode-connected to a ground.

Thus, it offers an advantage of being able to implement a compact andlow-loss phase shifter.

According to a third aspect of the present invention, there is provideda multiple-bit phase shifter having a phase shifter and a 180° bit phaseshifter used in combination with the phase shifter, the phase shiftercomprising: a first field effect transistor having its first channelelectrode connected to a first input/output terminal; a second fieldeffect transistor having its first channel electrode connected to asecond channel electrode of the first field effect transistor, and itssecond channel electrode connected to a second input/output terminal; athird field effect transistor having its first channel electrodeconnected to the second channel electrode of the first field effecttransistor; and an inductor having its first terminal connected to asecond channel electrode of the third field effect transistor, and itssecond terminal connected to a ground, wherein a circuit constant of thephase shifter is set such that an amount of phase shift becomes 90°.

Thus, it offers an advantage of being able to implement a compact andlow-loss multiple-bit phase shifter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a conventionalphase shifter;

FIG. 2 is an equivalent circuit diagram showing the operation of theconventional phase shifter;

FIG. 3 is an equivalent circuit diagram showing the operation of theconventional phase shifter;

FIG. 4 is a circuit diagram showing a configuration of a phase shifterof an embodiment 1 in accordance with the present invention;

FIG. 5 is a layout diagram showing the embodiment 1 of the phase shifterin accordance with the present invention;

FIG. 6 is an equivalent circuit diagram showing the operation of theembodiment 1 of the phase shifter in accordance with the presentinvention;

FIG. 7 is an equivalent circuit diagram showing the operation of theembodiment 1 of the phase shifter in accordance with the presentinvention;

FIG. 8 is a table showing filter characteristics;

FIG. 9 is a circuit diagram showing a configuration of a phase shifterof an embodiment 2 in accordance with the present invention;

FIG. 10 is a circuit diagram showing a configuration of a phase shifterof an embodiment 3 in accordance with the present invention;

FIG. 11 is a circuit diagram showing a configuration of a phase shifterof an embodiment 4 in accordance with the present invention;

FIG. 12 is a circuit diagram showing a configuration of a phase shifterof an embodiment 5 in accordance with the present invention;

FIG. 13 is a circuit diagram showing a configuration of a phase shifterof an embodiment 6 in accordance with the present invention;

FIG. 14 is a circuit diagram showing a configuration of a multiple-bitphase shifter of an embodiment 7 in accordance with the presentinvention; and

FIG. 15 is a circuit diagram showing a configuration of the multiple-bitphase shifter of an embodiment 8 in accordance with the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode for carrying out the invention will now be described withreference to the accompanying drawings to explain the invention in moredetail.

Embodiment 1

FIG. 4 is a circuit diagram showing a configuration of a phase shifterof an embodiment 1 in accordance with the present invention; and FIG. 5is a layout diagram showing the embodiment 1 of the phase shifter inaccordance with the present invention. In these figures, the referencenumeral 1 a designates an input/output terminal (first input/outputterminal); 1 b designates an input/output terminal (second input/outputterminal); 2 a designates an FET (first field effect transistor) havingits drain electrode, a first channel electrode, connected to theinput/output terminal 1 a; 2 b designates an FET (second field effecttransistor) having its drain electrode, a first channel electrode,connected to the source electrode of the FET 2 a, and its sourceelectrode, a second channel electrode, connected to the input/outputterminal 1 b.

The reference numeral 2 c designates an FET (third field effecttransistor) having its drain electrode, a first channel electrode,connected to the source electrode of the FET 2 a; 3 a designates aninductor having its first terminal connected to the source electrode ofthe FET 2 c, and its second terminal connected to the ground; referencenumerals 4 a, 4 b and 4 c each designate a resistor; 5 a and 5 b eachdesignate a control signal terminal; the reference numerals 6 designatesa semiconductor substrate; and 7 designates a through hole.

Next, the operation will be described.

FIGS. 6 and 7 are equivalent circuit diagrams each showing the operationof the phase shifter of the embodiment 1 in accordance with the presentinvention.

First, consider the case where the control signal terminal 5 a issupplied with a bias lower than the pinch-off voltage of the FETs 2 aand 2 b, and the control signal terminal 5 b is supplied with a biaslarger than the pinch-off voltage of the FET 2 c. In this case, the FETs2 a and 2 b are in the OFF-state and the FET 2 c is in the ON-state.Thus, the state across the drain and source of each of the FETs 2 a and2 b can be considered equivalent to a capacitor, and the state acrossthe drain and source of the FET 2 c can be considered equivalent to ashort circuit.

FIG. 6 is an equivalent circuit showing this state. In this state, thephase shifter operates as a T-type high-pass filter consisting of theFETs 2 a and 2 b equivalent to the capacitor and of the inductor 3 a.Thus, the phase of the high-frequency signal passing across theinput/output terminals 1 a and 1 b becomes an advanced state.

Next, consider the case where the FETs 2 a and 2 b are supplied with agate bias greater than the pinch-off, and the FET 2 c is supplied withthe gate bias less than the pinch-off. In this case, the FETs 2 a and 2b are in the ON-state and the FET 2 c is in the OFF-state. Thus, thestate across the drain and source of each of the FETs 2 a and 2 b can beconsidered equivalent to a short circuit, and the state across the drainand source of the FET 2 c can be considered equivalent a capacitor.

FIG. 7 is an equivalent circuit of this state. In this state, the phaseshifter operates as a circuit consisting of the FET 2 c equivalent to acapacitor and of the inductor 3 a. If the gate width of the FET 2 c isnarrowed to make the capacitance in the off state very small, the effectof the FET 2 c and inductor 3 a becomes negligible. Thus, the stateacross the input/output terminals 1 a and 1 b is nearly equivalent tothe through state.

As described above, the pass phase can be varied by placing the FETs 2a, 2 b and 2 c in the ON/OFF-state.

FIG. 8 is a table showing filter characteristics.

The conventional example uses a π-type high-pass filter, and the presentembodiment 1 employs a T-type high-pass filter. FIG. 8 compares theT-type high-pass filter with the π-type high-pass filter with equivalentfilter characteristics, to exhibit differences in the components and thelike. In FIG. 8, ω is an angular frequency, Cp is the OFF-statecapacitance of the FET 2 c, and θ is a desired phase shift amount.

To achieve equivalent filter characteristics, the T-type high-passfilter can reduce the inductance of the inductor and the number of theinductors as compared with the π-type high-pass filter. In addition, theT type can increase the capacitance of the high-pass filter, which isproportional to the size of the FETs 2 a and 2 b, as compared with the πtype. Accordingly, the T-type high-pass filter can reduce the loss bydecreasing the ON-state resistance of the FETs 2 a and 2 b. Furthermore,the π-type high-pass filter cannot achieve sufficient matching when itis in the state nearly equivalent to the through state because ofincreasing signal reflection due to the effect of the FET grounded viathe inductor. Thus, the present embodiment can achieve bettercharacteristics than the phase shifter using the conventional π-typehigh-pass filter.

Although the present embodiment 1 describes a monolithic structure thatforms a circuit on the semiconductor substrate 6, this is not essential.For example, the circuit can be configured on a dielectric substrateusing discrete components, offering equivalent advantages.

Although the drain electrode of the FET 2 a is connected to theinput/output terminal 1 a in the present embodiment 1, the sourceelectrode of the FET 2 a can be connected to the input/output terminal 1a. Likewise, although the source electrode of the FET 2 b is connectedto the input/output terminal 1 b, the drain electrode of the FET 2 b canbe connected to the input/output terminal 1 b. In addition, although thesource electrode of the FET 2 c is connected to the ground, the drainelectrode of the FET 2 c can be connected to the ground.

Embodiment 2

FIG. 9 is a circuit diagram showing a configuration of a phase shifterof an embodiment 2 in accordance with the present invention. In FIG. 9,the same portions as those of the phase shifter of FIG. 4 are designatedby the same reference numerals, and the description thereof is omittedhere. Although the phase shifter of the foregoing embodiment 1 isconfigured such that the FET 2 c is grounded through the inductor 3 a asshown in FIG. 4, the inductor 3 a can be grounded through the FET 2 c asshown in FIG. 9, offering the effect and advantages equivalent to thoseof the phase shifter of the foregoing embodiment 1.

Embodiment 3

FIG. 10 is a circuit diagram showing a configuration of a phase shifterof an embodiment 3 in accordance with the present invention. In FIG. 10,the same portions as those of the phase shifter of FIG. 4 are designatedby the same reference numerals, and the description thereof is omittedhere. In FIG. 10, the reference numeral 3 b designates an inductorconnected in parallel with the FET 2 c.

The phase shifter of the foregoing embodiment 1 brings the inductor 3 awhose one end is grounded into ON/OFF-state through the FET 2 c. Incontrast, the present embodiment 3 includes an additional inductor 3 bconnected in parallel with the FET 2 c as shown in FIG. 10 to form aparallel resonance circuit, thereby implementing a configurationachieving comparable effect and advantages by bringing the inductor 3 ainto ON/OFF-state.

Next, the operation will be described.

Consider the case where the FETs 2 a and 2 b are supplied with a gatebias greater than the pinch-off voltage, and the FET 2 c is suppliedwith a gate bias less than the pinch-off voltage. In this case, the FETs2 a and 2 b are in the ON-state and the FET 2 c is in the OFF-state.Accordingly, the state across the drain and source of each of the FETs 2a and 2 b can be considered equivalent to a short circuit, and the stateacross the drain and source of the FET 2 c can be considered equivalentto a capacitor.

In this state, causing the FET 2 c and inductor 3 b to produce parallelresonance at a desired frequency can reduce the effect of the inductor 3a so that the inductor 3 a becomes negligible. In this case, the stateacross the input/output terminals 1 a and 1 b becomes equivalent to thethrough state.

As described above, bringing the FETs 2 a and 2 b into the ON-state andthe FET 2 c into the OFF-state enables the phase shifter to vary thepass phase.

Embodiment 4

FIG. 11 is a circuit diagram showing a configuration of a phase shifterof an embodiment 4 in accordance with the present invention. In FIG. 11,the same portions as those of the phase shifters of FIGS. 4 and 10 aredesignated by the same reference numerals, and the description thereofis omitted here.

The relationship of the connection of the inductor 3 a with the FET 2 cand inductor 3 b as shown in the FIG. 10 can be reversed as shown inFIG. 11, offering comparable effect and advantages. In addition,comparable effect and advantages can be achieved by connecting theinductor 3 b to both sides of the FET 2 c and inductor 3 a (not shown).

Embodiment 5

FIG. 12 is a circuit diagram showing a configuration of a phase shifterof an embodiment 5 in accordance with the present invention. In FIG. 12,the same portions as those of the phase shifters of FIGS. 4 and 10 aredesignated by the same reference numerals, and the description thereofis omitted here. In FIG. 12, the reference numeral 8 a designates acapacitor connected in parallel with the FET 2 a, and 8 b designates acapacitor connected in parallel with the FET 2 b.

In the foregoing embodiment 1, although the FETs 2 a and 2 b are used asthe capacitors for varying the pass phase in the high-pass filter, thisis not essential. For example, the configuration as shown in FIG. 12,which connects the capacitors 8 a and 8 b in parallel with the FETs 2 aand 2 b, can implement comparable effect and advantages.

Next, the operation will be described.

First, consider the case where the control signal terminal 5 a issupplied with a gate bias lower than the pinch-off voltage of the FETs 2a and 2 b, and the control signal terminal 5 b is supplied with a gatebias greater than the pinch-off voltage of the FET 2 c, so that the FETs2 a and 2 b are in the OFF-state and the FET 2 c is in the ON-state. Inthis case, the state across the drain and source of each of the FETs 2 aand 2 b can be considered equivalent to a capacitor, and the stateacross the drain and source of the FET 2 c can be considered equivalentto a short circuit. Thus, the phase shifter operates as a T-typehigh-pass filter consisting of the FETs 2 a and 2 b equivalent to thecapacitors, capacitors 8 a and 8 b, and inductor 3 a.

As described above, turning on and off the FETs 2 a, 2 b and 2 c enablesthe phase shifter to vary the phase of the pass signal.

In addition, when the capacitance per unit area of the capacitors 8 aand 8 b is greater than that of the FETs 2 a and 2 b, the presentembodiment 5 can reduce its size as compared with the case where thesecapacitors are implemented by using only the FETs 2 a and 2 b.

Furthermore, varying the size with maintaining the total capacitance ofthe FET 2 a and capacitor 8 a and the total capacitance of the FET 2 band capacitor 8 b makes it possible to vary the ON-state resistance ofthe FETs 2 a and 2 b, and hence the insertion loss with maintaining theamount of phase shift, thereby being able to reduce the loss differenceat the phase switching.

Embodiment 6

FIG. 13 is a circuit diagram showing a configuration of a phase shifterof an embodiment 6 in accordance with the present invention. In FIG. 13,the same portions as those of the phase shifters of FIGS. 4 and 10 aredesignated by the same reference numerals, and the description thereofis omitted here. In FIG. 13, the reference numeral 8 c designates acapacitor connected in parallel with the FET 2 c.

Although the foregoing embodiment 5 handles the configuration in whichthe capacitors 8 a and 8 b are connected in parallel with the FETs 2 aand 2 b that are connected to the input/output terminals 1 a and 1 b,this is not essential. For example, connecting the capacitor 8 c inparallel with the FET 2 c and inductor 3 b for turning on and off theinductor 3 a whose one end is grounded can implement comparable effectand advantages.

Next, the operation will be described.

Consider the case where the FETs 2 a and 2 b are supplied with a gatebias greater than the pinch-off voltage, and the FET 2 c is suppliedwith a gate bias less than the pinch-off voltage. In this case, the FETs2 a and 2 b are in the ON-state and the FET 2 c is in the OFF-state.Accordingly, the state across the drain and source of each of the FETs 2a and 2 b can be considered equivalent to a short circuit, and the stateacross the drain and source of the FET 2 c can be considered equivalentto a capacitor. In this state, causing the FET 2 c, inductor 3 b andcapacitor 8 c to produce parallel resonance at a desired frequency canreduce the effect of the inductors 3 a and 3 b to a level they arenegligible.

As described above, bringing the FETs 2 a, 2 b and 2 c into theON/OFF-state enables the phase shifter to vary the phase of the passsignal.

In addition, when the capacitance per unit area of the capacitor 8 c isgreater than that of the FET 2 c, the present embodiment 6 can reduceits size as compared with the case where the capacitor is implemented byusing only the FET 2 c.

Furthermore, varying the size of the FET 2 c and capacitor 8 c withmaintaining their total capacitance makes it possible to vary theinsertion loss with maintaining the amount of phase shift, therebyenabling the reduction in the loss difference at the phase switching.

Embodiment 7

FIG. 14 is a circuit diagram showing a configuration of a multiple-bitphase shifter of an embodiment 7 in accordance with the presentinvention. In FIG. 14, reference numerals 20 a and 20 b each designatean SPDT switch, the reference numeral 21 designates a high-pass filter,22 designates a low-pass filter, 23 designates a 180° bit phase shifter,and 24 designates a 90° bit phase shifter. The 90° bit phase shifter 24can use the phase shifter of the embodiments 1–6, for example. The phaseshifter 24 as shown in FIG. 14 is an example using the phase shifter ofthe embodiment 3.

Next, the operation will be described.

The path, through which the high-frequency signal supplied to theinput/output terminal 1 a passes, is switched by the SPDT switches 20 aand 20 b. First, when it passes through the high-pass filter 21, thepass phase is advanced by the high-pass filter 21. In contrast, when itpasses through the low-pass filter 21, the pass phase is delayed by thelow-pass filter 22. Setting the phase difference between the phaseadvanced by the high-pass filter 21 and the phase delayed by thelow-pass filter 22 at 180° enables a 180° phase shifter.

Next, setting the circuit constant of the 90° bit phase shifter suchthat the amount of phase shift becomes 90°, the 90° phase shifter 24 canshift the phase by 90°.

With the configuration as described above, the multiple-bit phaseshifter of the embodiment 7 operates as a 2-bit phase shifter thatswitches its pass phase at 90° steps.

Embodiment 8

FIG. 15 is a circuit diagram showing a configuration of a multiple-bitphase shifter of an embodiment 8 in accordance with the presentinvention. In FIG. 15, the same portions as those of the multiple-bitphase shifter of FIG. 14 are designated by the same reference numerals,and the description thereof is omitted here. In FIG. 15, the referencenumeral 25 designates a 45° bit phase shifter, 26 designates a 22.5° bitphase shifter, and 27 designates an 11.25° bit phase shifter. Althoughthe phase shifters 24 and 25 of the multiple-bit phase shifter as shownin FIG. 15 are an example using the phase shifter of the embodiment 3,they can use any of the phase shifters of the embodiments 1–6.

With the configuration, the multiple-bit phase shifter of the embodiment8 operates as a 5-bit phase shifter that switches the pass phase by11.250 ° steps.

INDUSTRIAL APPLICABILITY

As described above, the phase shifter and multiple-bit phase shifter inaccordance with the present invention are-suitable for shifting thephase of a high-frequency signal with reducing the insertion loss andachieving the sufficient matching with reducing the reflection of thesignal.

1. A phase shifter comprising: a first field effect transistor havingits first channel electrode directly connected to a first input/outputterminal; a second field effect transistor having its first channelelectrode directly connected to a second channel electrode of said firstfield effect transistor, and its second channel electrode connecteddirectly to a second input/output terminal; a third field effecttransistor having its first channel electrode connected directly to thesecond channel electrode of said first field effect transistor; a firstinductor having its first terminal connected to a second channelelectrode of said third field effect transistor, and its second terminalconnected directly to a ground; a first resistor connected to a gate ofthe first field effect transistor; a second resistor connected to a gateof the second field effect transistor, the first resistor and secondresistor being connected in parallel; a third resistor connected to agate of the third field effect transistor; and a second inductorconnected between the first channel electrode and second channelelectrode of said third field effect transistor.
 2. The phase shifteraccording to claim 1, further comprising a capacitor connected betweenthe first channel electrode and second channel electrode of each of saidfirst and second field effect transistors.
 3. The phase shifteraccording to claim 1, further comprising a capacitor connected betweenthe first channel electrode and second channel electrode of said thirdfield effect transistor.
 4. The phase shifter according to claim 1,wherein a circuit constant is set such that an amount of a phase shiftbecomes 90°.
 5. The phase shifter according to claim 1, wherein acircuit constant is set such that an amount of phase shift becomes 45°.6. A phase shifter comprising: a first field effect transistor havingits first channel electrode directly connected to a first input/outputterminal; a second field effect transistor having its first channelelectrode connected directly to a second channel electrode of said firstfield effect transistor, and its second channel electrode connecteddirectly to a second input/output terminal; a first inductor having itsfirst terminal directly connected to the second channel electrode ofsaid first field effect transistor; a third field effect transistorhaving its first channel electrode directly connected to a secondterminal of said first inductor, and its second channel electrodedirectly connected to a ground; a first resistor connected to a gate ofthe first field effect transistor; a second resistor connected to a gateof the second field effect transistor, the first resistor and secondresistor being connected in parallel; a third resistor connected to agate of the third field effect transistor; and a second inductorconnected between the first channel electrode and second channelelectrode of said third field effect transistor.
 7. The phase shifteraccording to claim 6, further comprising a capacitor connected betweenthe first channel electrode and second channel electrode of each of saidfirst and second field effect transistors.
 8. The phase shifteraccording to claim 6, further comprising a capacitor connected betweenthe first channel electrode and second channel electrode of said thirdfield effect transistor.
 9. The phase shifter according to claim 6,wherein a circuit constant is set such that an amount of phase shiftbecomes 90°.
 10. The phase shifter according to claim 6, wherein acircuit constant is set such that an amount of phase shift becomes 45°.